1. Field of the Invention
The present invention is related to a voltage regulator for a memory, and more particularly, to a voltage regulator for a memory capable of stabilizing output voltages.
2. Description of the Prior Art
While semiconductor technology continuously reduces size to achieve bigger storage, a voltage regulator on a chip has to be able to provide lower supply voltage to an inner circuit in order to increase reliability and reducing power consumption of memory. For bit-line sensing in dynamic random access memory (DRAM), both recovery and pre-charge of a memory unit array consume current abruptly and severely. Therefore, devising a voltage regulator on a chip provides stable voltage level with sufficient and proper supply current to the memory unit array.
Please refer to FIG. 1, which illustrates a schematic diagram of a voltage regulator for memory according to the prior art. A voltage regulator 100 includes a first transistor 111, a second transistor 112, an inductor 151, a digital boosting control circuit and an analog boosting control circuit. The digital boosting control circuit includes a first control unit 141. The analog boosting control circuit includes a third transistor 113, a feedback unit 120, a comparison unit 130 and a second control unit 142. A first end of the inductor 151 is electrically connected to a voltage source VDD, and a second end of the inductor 151 is electrically connected to an input node N1. The first transistor 111 is a P-type Metal Oxide Semiconductor (PMOS) transistor. A first end of the first transistor 111 is electrically connected to the input node N1, a second end of the first transistor 111 is electrically connected to an output node N2, and a control end of the first transistor 111 is electrically connected to the comparison unit 130. The second transistor 112 is a PMOS transistor. A first end of the second transistor 112 is electrically connected to the input node N1, a second end of the second transistor 112 is electrically connected to the output node N2, and a control end of the second transistor 112 is electrically connected to the first control unit 141. The third transistor 113 is an N-type Metal Oxide Semiconductor (NMOS) transistor. A first end of the third transistor 113 is electrically connected to the control end of the first transistor 113, a second end of the third transistor 113 is electrically connected to a ground end, and a control end of the third transistor 113 is electrically connected to the second control unit 142. The feedback unit 120 includes resistors 121 and 122. Voltage VCCSA at the output node N2 can generate a feedback signal VFB via the resistors 121 and 122. The comparison unit 130 includes an operational amplifier 131. The comparison unit 110 compares the feedback signal VFB with a reference voltage REF to generate a control signal PDRV_ACT for controlling the first transistor 111, to stabilize the voltage VCCSA at the output node N2. The output node N2 of the voltage regulator 100 is electrically connected to the sensing amplifier 160 of the memory, for providing the stabilized voltage VCCSA. The inductor 152 is electrically connected to the sensing amplifier 160. The first control unit 141 generates a first control signal A for controlling the second transistor 112 according to an input signal IN, and the second control unit 142 generates a second control signal B for controlling the third transistor 113 according to the input signal IN.
Please refer to FIG. 2, which illustrates a schematic diagram of operation waveforms shown in FIG. 1. The first control unit 141 generates the first control signal A according to the input signal IN. When the input signal IN rises from a low level L to a high level H, the first control signal A drops from the high level H to the low level L, which turns on the second transistor 112. Meanwhile, current flows from the input node N1 to the output node N2 via the second transistor 112, and thus the voltage VDDSA at the input node N1 drops, the voltage VCCSA at the output node N2 rises. The second control unit 142 generates the second control signal B according to the input signal IN. When the first control signal A is at the low level L, the second control signal B turns on the third transistor 113, such that the control end of first transistor 111 is electrically connected to the ground end. Therefore the control signal PDRV_ACT is pulled to the low level L, while the first transistor 111 is fully turned on. When the third transistor 113 is turned off, the control signal PDRV_ACT is determined by the comparison unit 110. However, the control signal PDRV_ACT changes according to the voltage VCCSA at the node N2. Hence, when the signal A changes, oscillation may occur on the voltage VDDSA at the node N1, causing current dis-continuousity, and the voltage VCCSA at the output node N2 may become higher and higher, or a high voltage drop may be generated at the output node N2. Besides, improperly design of the size of the second transistor 112 or signal widths of the control signal A and B can also cause the discontinuity of the current. As can be seen from the above, the voltage regulator 100 of the prior art mainly initiates the analog boosting control circuit and the digital boosting control circuit at the same time. However, at high voltages, with the driving of the digital boosting control circuit, pulse width may be too long, which causes feedback failure, generating the oscillations.